• DocumentCode
    2370945
  • Title

    Reducing leakage with mixed-Vth (MVT)

  • Author

    Sill, Frank ; Grassert, Frank ; Timmermann, Dirk

  • Author_Institution
    Rostock Univ., Germany
  • fYear
    2005
  • fDate
    3-7 Jan. 2005
  • Firstpage
    874
  • Lastpage
    877
  • Abstract
    We present a new method for assignment of devices with different Vth in a double-Vth-process, whereas leakage is reduced and performance increases or is constant. A mixed-Vth gate type is developed, which renders new masks unnecessary. As compared with known methods, our approach achieves an additional leakage reduction of 25% while leakage reduction in raw designs is average 65%.
  • Keywords
    CMOS integrated circuits; integrated circuit design; leakage currents; low-power electronics; double-Vth-process; leakage reduction; mixed-Vth gate type; Delay effects; Design optimization; Doping; Dynamic voltage scaling; Leakage current; Power dissipation; Semiconductor device modeling; Subthreshold current; Threshold voltage; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2005. 18th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2264-5
  • Type

    conf

  • DOI
    10.1109/ICVD.2005.147
  • Filename
    1383391
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2370945