A partial scan algorithm based on reduced scan shift

This paper presents a partial scan algorithm, called PARES (Partial scan Algorithm based on REduced Scan shift), which designs partial scan circuits and generates short test sequences. PARES is based on the reduced scan shift, in which flip flops (FFs) required to be controlled and observed are determined for each test vector in order to reduce scan shift operations. PARES selects FFs which are more frequently required to be controlled or observed as a scanned FF. Short test sequence can be obtained by reducing scan shift operations. Since fault coverage may be not possibly high because of unscanned FFs, techniques to increase fault coverage are also proposed. The order of test vectors are determined such that the values of unscanned FFs after applying a test vector is equivalent to next applied test vector. Moreover, appropriate values are assigned to primary inputs in scan shift operations in order to detect more faults. Finally experimental results for ISCAS´89 benchmark circuits are given