Test time reduction for scan-designed circuits by sliding compatibility

A post generation method for test time reduction of scan-designed circuits is developed in this paper. Maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity-scan, the test clocks required by our developed method are only 41% of those reported by H. Fujiwara and A. Yamamoto (1993)