DocumentCode
2371300
Title
Testable synthesis and testing of finite state machines
Author
Liu, Chun-Yeh ; Saluja, Kewal K.
Author_Institution
Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
fYear
1994
fDate
15-17 Nov 1994
Firstpage
305
Lastpage
310
Abstract
In this paper, me outline a method for testable synthesis of finite state machines (FSMs). We address the design for testability issue for testing FSMs with and without scan. The experimental results on the MCNC benchmarks show that our designs are 100% testable with small to moderate increase in area
Keywords
design for testability; finite state machines; logic testing; programmable logic arrays; sequential circuits; MCNC benchmarks; PLA; design for testability; finite state machines; sequential circuits; state assignment; testable synthesis; Automata; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Design for testability; Logic circuits; Logic testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location
Nara
Print_ISBN
0-8186-6690-0
Type
conf
DOI
10.1109/ATS.1994.367214
Filename
367214
Link To Document