Title :
Automatic program generator for simulation-based processor verification
Author :
Iwashita, Hiroaki ; Kowatari, Satoshi ; Nakata, Tsuneo ; Hirose, Fumiyasu
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
This paper presents an efficient test program generator for logic simulation that uses techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for any reachable test case. The program covers all complicated test cases that are difficult to cover with random instructions and are impossible to cover by conventional test program generation methods
Keywords :
automatic programming; automatic test software; computer testing; logic CAD; logic testing; pipeline processing; random processes; automatic program generator; formal verification; instruction sequences; logic simulation; processor pipeline; random instructions; reachable test case; simulation-based processor verification; test program generator; Automatic programming; Clocks; Hardware; Hazards; Laboratories; Logic design; Logic testing; Microprocessors; Pipelines; System testing;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367215
