A unified method for assembling global test schedules

Author

Stroele, Albrecht P. ; Wunderlich, Hans-Joachim

Author_Institution

Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany

fYear

1994

fDate

15-17 Nov 1994

Firstpage

268

Lastpage

273

Abstract

In order to make a register transfer structure testable, it is usually divided into functional blocks that can be tested independently by various test methods. The test patterns are shifted in or generated autonomously at the inputs of each block. The test responses of a block are compacted or observed at its output register. In this paper a unified method for assembling all the single tests to a global schedule is presented. It is compatible with a variety of different test methods. The described scheduling procedures reduce the overall test time and minimize the number of internal registers that have to be made directly observable

Keywords

built-in self test; design for testability; integrated circuit testing; integrated logic circuits; logic testing; performance evaluation; scheduling; shift registers; built in self test; data path; design for testability; functional blocks; global schedule; global test schedules; internal registers; minimisation; observability; register transfer structure; scheduling; test patterns; test responses; test scheduling; test time; unified method; Assembly; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Hardware; Logic testing; Processor scheduling; Registers; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367220

Filename

367220