DocumentCode
237142
Title
A Real-Time Instruction Cache with High Average-Case Performance
Author
Yijie Huangfu ; Wei Zhang
Author_Institution
Compiler, Archit., & Realtime Syst. (CARS) Lab., Virginia Commonwealth Univ., Richmond, VA, USA
fYear
2014
fDate
10-12 June 2014
Firstpage
109
Lastpage
116
Abstract
Cache memories, while useful for improving the average-case performance for general-purpose applications, are not suitable for real-time systems due to the time unpredictability. In this paper, we propose a Performance Enhancement Guaranteed Cache (PEG-C) to ensure performance improvement in the worst case while achieving as good average-case performance as a regular hardware-controlled cache. We design and evaluate an instruction PEG-C as a proof-of-concept. Our experiments indicate that with a small number of preloaded instructions, the PEG instruction cache can achieve the same performanceas a regular instruction cache, and outperform cache locking significantly.
Keywords
cache storage; performance evaluation; PEG instruction cache; PEG-C; cache locking; cache memories; general-purpose applications; hardware-controlled cache; high average-case performance; performance enhancement guaranteed cache; preloaded instructions; real-time instruction cache; regular instruction cache; Benchmark testing; Computer architecture; Hardware; Program processors; Radiation detectors; Real-time systems; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), 2014 IEEE 17th International Symposium on
Conference_Location
Reno, NV
ISSN
1555-0885
Type
conf
DOI
10.1109/ISORC.2014.59
Filename
6899138
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