Title :
A 1V CMOS PLL designed in high-leakage CMOS process operating at 10-700MHz
Author_Institution :
Analog Devices Inc., DSP Design Center
Keywords :
CMOS process; Capacitance; Capacitors; Charge pumps; Feedback; Frequency; Jitter; Leakage current; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992223
