Selecting programmable space compactors for BIST using genetic algorithms

With the increasing complexity of modern VLSI circuits, achieving high duality (off-line) built-in self-test requires monitoring an increasingly large number of internal nodes. Due to the limitations in observing large numbers of nodes, it has become increasingly necessary to compact the output from a large number of lines to a small number of lines in a process known as space compaction. Recently, a class of circuit-specific space compactors, known as programmable space compactors (PSCs), has been proposed. Circuit-specific information such as the fault-free and expected faulty behaviour of a circuit can be used to choose PSCs that have better fault coverage and/or lower area costs than the parity function. A drawback of PSCs is the difficulty involved in finding optimal PSCs for a circuit, since the space of possible PSC functions is extremely large and grows exponentially with the number of lines to be compacted. This paper proposes a method for searching for combinational PSCs based upon genetic algorithms. The factors used to assess the effectiveness, or fitness, of a PSC are its fault coverage (estimated by the probability of aliasing) and area. Searches based upon genetic algorithms can find PSCs with better fault coverage and cost characteristics than the parity function using modest computing resources. PSCs with equal or greater fault coverage than the parity function for as little as 20% of the cost (in terms of gate count) were found with an investment of only a few hours of workstation computing time