Title :
Design of random pattern testable floating point adders
Author :
Rajski, J. ; Tyszer, J.
Author_Institution :
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
The paper presents a floating point adder with enhanced testability and test response compaction capabilities. It is shown that the testability of the conventional adders can be improved by changing the functionality of some of their internal modules in the testing mode. It is also demonstrated that the floating point units can perform an efficient test response compaction in a built-in self test environment
Keywords :
adders; built-in self test; design for testability; digital simulation; floating point arithmetic; logic design; modules; shift registers; built-in self test environment; enhanced testability; floating point accumulator; floating point units; functionality; internal modules; random pattern testable floating point adders; rotate shifter; simulation experiments; test response compaction; testability; Adders; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Information analysis; Information theory; Pattern analysis; Performance evaluation;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367226
