DocumentCode
2371574
Title
A new testable design of logic circuits under highly observable condition
Author
Xiaoqing, Wen ; Tamamoto, Hideo ; Kinoshita, Kozo
Author_Institution
Min. Coll., Akita Univ., Japan
fYear
1994
fDate
15-17 Nov 1994
Firstpage
195
Lastpage
200
Abstract
This paper presents the concept of k-FR circuits. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k+1)+1 tests render the highly observable condition. K is usually two or three. The paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit
Keywords
combinational circuits; design for testability; fault diagnosis; fault location; logic design; logic testing; circuit conversion; combinational circuit; k-FR circuits; k-balance conversion; k-maximum conversion; logic circuits; stuck-at faults; stuck-open faults; testable design; Circuit faults; Circuit testing; Combinational circuits; Current measurement; Educational institutions; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Physics;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location
Nara
Print_ISBN
0-8186-6690-0
Type
conf
DOI
10.1109/ATS.1994.367231
Filename
367231
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