Aspect-Oriented Model-Driven Engineering for FPGA/VHDL Based Embedded Real-Time Systems

This work aims to assist the design of FPGA-based embedded system by extending the AMoDE-RT approach in order to support automatic generation of VHDL descriptions from high-level specification of embedded systems. This paper discusses the handling of non-functional requirements using concepts from Aspect-Oriented Software Development (AOSD) paradigm. The proposed approach promotes the specification of platform-independent aspects in UML/MARTE model, which is later used to generate the system VHDL description. A set of mapping rules has been created to implement the model-level aspects using VHDL constructs/statements. GenERTiCA tool has been extended to allow the UML-to-VHDL automatic transformation, including the weaving of aspects adaptations code into the generated VHDL description. Such an approach allows not only the generation of a fully sinthesizable VHDL description, but also the reuse of aspects in distinct implementation technologies. The obtained results show an increase in system performance and a better utilization of FPGA configurable resources due to the improved components modularization. These results indicate the practicability of full translation of platform-independent aspects into VHDL, opening room for gains in embedded real-time system design, including reuse and design effort reduction.