Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement

We systematically studied short-channel mobility (μ) in SOI nanowire transistors (NW Tr.). The strain induced in the NW channel dominates short-L μ. μ of short-L <;110>; NW nFETs largely increases due to vertical compressive strain. We achieved further strain enhancement in NW channel by stress memorization technique (SMT). μ increase by SMT is much larger in NW Tr. than in planar Tr. In <;110>; NW nFETs, I_on on the same DIBL increases by as much as 58% by SMT thanks to significant R_SD reduction in addition to μ increase, while I_on degradation of pFETs is minimal.