An approach of diagnosing single bridging faults in CMOS combinational circuits

Author

Yamazaki, Koji ; Yamada, Teruhiko

Author_Institution

Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

fYear

1994

fDate

15-17 Nov 1994

Firstpage

88

Lastpage

93

Abstract

An approach of diagnosing single bridging faults in CMOS combinational circuits is proposed. In this approach, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is proportional to [the number of gates]×[the number of tests], which is much smaller than that of the fault dictionary. The experimental results show that the CPU time is nearly proportional to the size of the circuit and the resolutions for most faults are less than 100, when using the tests to detect single stuck-at faults

Keywords

CMOS integrated circuits; automatic testing; combinational circuits; fault diagnosis; fault location; logic testing; performance evaluation; ASIC; CMOS combinational circuits; diagnosis table; performance evaluation; primary outputs; single bridging faults; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Dictionaries; Fault diagnosis; Semiconductor device modeling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367248

Filename

367248