Title :
An efficient logical fault diagnosis for combinational circuits using stuck-at fault simulation
Author_Institution :
Comput. Div., NEC Corp.
Abstract :
A new efficient method to diagnose faults in a gate or function block is proposed. This method can localize a single logic function fault, which is caused by internal stuck-at, short or open faults in the gate or function block, by using stuck-at fault simulation. Since a practical fault diagnostic system is now under development the effectiveness of the method is demonstrated by experimental results on the ISCAS´85 benchmark circuits
Keywords :
VLSI; automatic testing; combinational circuits; fault diagnosis; fault location; integrated circuit testing; integrated logic circuits; logic testing; performance evaluation; ISCAS´85 benchmark circuits; VLSI; combinational circuits; effectiveness; experimental results; logic function fault; logical fault diagnosis; short circuit faults; stuck-at fault simulation; stuck-at faults; Circuit faults; Circuit simulation; Combinational circuits; Computational modeling; Fault diagnosis; Logic functions; Logic testing; Probes; Very large scale integration; Wiring;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367250
