On the performance analysis of parallel processing for test generation

Author

Inoue, Tomoo ; Fujii, Takaharu ; Fujiwara, Hideo

Author_Institution

Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan

fYear

1994

fDate

15-17 Nov 1994

Firstpage

69

Lastpage

74

Abstract

The performance of parallel processing for test generation depends on the method of communication among processors. This paper presents two types of parallel processing which differ in communication methods, and analyzes their performance. We formulate the number of test vectors obtained in parallel processing, and analyze the costs of test generation, fault simulation and interprocessor communication and the speedup ratio. Further, we consider a method which minimizes the cost of interprocessor communication

Keywords

VLSI; automatic testing; communication complexity; computational complexity; fault location; integrated circuit testing; minimisation; multiprocessing systems; multiprocessor interconnection networks; parallel processing; performance evaluation; costs; fault simulation; interprocessor communication; parallel processing; performance analysis; speedup ratio; test generation; test vectors; Analytical models; Circuit faults; Circuit testing; Costs; Fault detection; Information science; Multiprocessing systems; Parallel processing; Performance analysis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367251

Filename

367251