Title :
Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation
Author :
Hahn, W. ; Hagerer, A.
Author_Institution :
Fac. of Math. & Comput. Sci., Passau Univ., Germany
Abstract :
The Munich Simulation Computer, a highly-parallel system, has been an approach to speed up logic simulation. Most recent work, presented in this paper, has been devoted to hardware-accelerated concurrent fault simulation. By the new parallel-pattern/multiple-fault-propagation algorithm, a MuSiC version with 256 processing units can offer a simulation performance of 108 test-vectors times gates evaluated per second
Keywords :
VLSI; discrete event simulation; fault diagnosis; integrated circuit testing; logic CAD; logic testing; parallel architectures; MuSiC version; Munich Simulation Computer; event flow computing; hardware-accelerated concurrent fault simulation; logic simulation; parallel-pattern multiple-fault-propagation concurrent fault simulation; test-vectors; update dataflow computing; Acceleration; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer architecture; Computer simulation; Concurrent computing; Logic; Parallel processing;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367261
