DocumentCode :
2372383
Title :
Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study
Author :
Karlström, Per ; Zhou, Wenbiao ; Liu, Dake
Author_Institution :
Dept. of EE, Linkoping Univ., Linköping, Sweden
fYear :
2010
fDate :
11-13 Dec. 2010
Firstpage :
68
Lastpage :
72
Abstract :
Flexible Application Specific Instruction-set Processors (ASIPs) are starting to replace monolithic Application Specific Integrated Circuits (ASICs) in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. Novel Generator of Accelerators And Processors (NoGap) is a tool for ASIP design utilizing hardware multiplexed data paths. One of the main advantages of NoGap compared to other EDA tools for processor design, is that NoGap imposes few limits on the architecture and thus design freedom. To prove that NoGap can be used to design complex data paths a reimplementation of a floating point adder/subtracter previously implemented using Verilog with FPGA specific optimizations was reimplemented using the NoGap Common Language (NoGapCL). The adder/subtracter implemented in Verilog can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12) as compared with the NoGap implementation which had a maximum operation frequency of 276 Mhz, using the hand optimized mantissa adder from the original Verilog code, the NoGap implementation reached timing closure at 326 Mhz.
Keywords :
electronic design automation; field programmable gate arrays; floating point arithmetic; hardware description languages; NoGap common language; NoGap tool; Verilog; application specific instruction-set processors; application specific integrated circuits; electronic design automation; field programmable gate array; floating point adder; floating point subtracter; hardware multiplexed data paths; novel generator of accelerators and processors; ADL; Accelerator; DSP; Floating point; Processor; RTL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded and Ubiquitous Computing (EUC), 2010 IEEE/IFIP 8th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-9719-5
Electronic_ISBN :
978-0-7695-4322-2
Type :
conf
DOI :
10.1109/EUC.2010.20
Filename :
5703500
Link To Document :
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