DocumentCode

2372529

Title

A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

Author

Rogenmoser, R. ; O´Donnell, L. ; Nishimoto, S.

Author_Institution

Broadcom

Volume

2

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

336

Lastpage

536

Keywords

Adders; Central Processing Unit; Circuits; Clocks; Coprocessors; Decoding; Delay; MOS devices; Read only memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992283

Filename

992283