Hardware-Software Co-design of a Fingerprint Image Enhancement Algorithm

This paper presents the implementation of a fingerprint image enhancement algorithm on a FPGA device. The design is based on a hardware-software co-design, which consists of a dedicated coprocessor that solves the parts of the algorithm with higher computational cost and an embedded microprocessor that manages the control process and executes the rest of the algorithm. In order to develop an efficient implementation, fixed-point computations have substituted the floating-point ones. The system has been implemented on a Xilinx Spartan 3 FPGA, with an external SRAM memory of 512Ktimes32 bits and using a Microblaze embedded soft-core processor. Results show that a 256times256 pixel image can be analyzed in 750 ms with a clock frequency of 50 MHz