Title :
Yield and routing objectives in floorplanning
Author :
Koren, Israel ; Koren, Zahava
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Traditionally the floorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the floorplan also affects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to study the two seemingly disjoint objectives of yield enhancement and routing complexity minimization, and find out whether they lead to different optimal floorplans, resulting in a need for a tradeoff analysis
Keywords :
circuit layout CAD; integrated circuit layout; integrated circuit yield; modules; network routing; disjoint objectives; expected yield; floorplanning; routing complexity; routing objectives; total chip area; tradeoff analysis; yield enhancement; Arithmetic; Contracts; Cost function; Decoding; Delay; Integrated circuit yield; Logic; Microprocessors; Routing; Wiring;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732148
