Title :
Orphan metal removal as an element of DFM
Author_Institution :
Philips Semicond., Albuqerque, NM, USA
Abstract :
Discussion of improving the yield and manufacturability of designs through the modification of metal tracks has apparently neglected a potentially important first step-that of removal of metal which is surplus to the design. A technique is described for the identification and removal of surplus or `orphan´ metal using tools present in the Cadence layout system. Application of this technique to a semi-custom product designed in a 0.8 micron analog BiCMOS process is outlined
Keywords :
BiCMOS analogue integrated circuits; application specific integrated circuits; design for manufacture; integrated circuit design; integrated circuit layout; integrated circuit metallisation; integrated circuit yield; 0.8 micron; Cadence layout system; DFM; analog BiCMOS process; manufacturability; metal tracks; orphan metal removal; semi-custom product; yield; Circuits; Design for manufacture; Routing; Surface topography; Yield estimation;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732149
