Title :
Accurate fault modeling and fault simulation of resistive bridges
Author :
Sar-Dessai, Vijay ; Walker, D.M.H.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We show that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zeroohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults
Keywords :
VLSI; combinational circuits; fault simulation; integrated circuit testing; logic testing; ISCAS85 benchmark circuits; coverage metric; fault modeling; fault simulation; gate level combinational circuits; resistive bridging faults; voltage-testable bridging faults; zeroohm bridge fault model; Bridge circuits; Circuit faults; Circuit simulation; Computational modeling; Fault detection; Integrated circuit modeling; Logic gates; Power supplies; Threshold voltage; Voting;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732156
