Title :
Functional verification coverage vs. physical stuck-at fault coverage
Author :
Sun, Xiao ; Hull, Carmie
Author_Institution :
Semicond. Product Sector, Motorola Inc., Austin, TX, USA
Abstract :
It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage
Keywords :
VLSI; fault diagnosis; integrated circuit testing; logic testing; functional property model; functional verification coverage; nonredundant physical stuck-at faults; physical stuck-at fault coverage; short verification; test application time; Acoustic testing; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Sun; Telephony;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732157
