• DocumentCode
    2373652
  • Title

    Functional verification coverage vs. physical stuck-at fault coverage

  • Author

    Sun, Xiao ; Hull, Carmie

  • Author_Institution
    Semicond. Product Sector, Motorola Inc., Austin, TX, USA
  • fYear
    1998
  • fDate
    2-4 Nov 1998
  • Firstpage
    108
  • Lastpage
    116
  • Abstract
    It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage
  • Keywords
    VLSI; fault diagnosis; integrated circuit testing; logic testing; functional property model; functional verification coverage; nonredundant physical stuck-at faults; physical stuck-at fault coverage; short verification; test application time; Acoustic testing; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Sun; Telephony;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
  • Conference_Location
    Austin, TX
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-8832-7
  • Type

    conf

  • DOI
    10.1109/DFTVS.1998.732157
  • Filename
    732157