Title :
On the complexity of sequential testing in configurable FPGAs
Author :
Feng, W. ; Huang, W.-K. ; Meyer, F.J. ; Lombardi, F.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper addresses the issues pertaining to testing field programmable gate arrays (FPGAs) using an array-based technique. In particular, the issues of testing configurable devices (such as multiplexers and flip-flops) in the sequential array process (as the most significant factor for assessing complexity) and the arrangement for pipelining test vectors are treated in detail. Initially testing procedures for a configurable flip-flop and a programmable multiplexer are presented. At system-level, two new pipeline arrangements referred to as the quasi-pipeline and normal pipeline structures are proposed for reducing the number of programming phases. The application of the proposed approaches to the XC4000 FPGA family is also presented
Keywords :
field programmable gate arrays; flip-flops; integrated circuit testing; logic testing; multiplexing equipment; sequential circuits; XC4000 FPGA family; array-based technique; configurable FPGAs; flip-flops; multiplexers; normal pipeline; pipelining; quasi-pipeline; sequential testing; test vectors; Built-in self-test; Circuit testing; Field programmable gate arrays; Logic arrays; Logic programming; Logic testing; Multiplexing; Pipeline processing; Programmable logic arrays; Sequential analysis;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732163
