Title :
Diagnosis of scan chain failures
Author_Institution :
Northern Telecom Electron. Ltd., Ottawa, Ont., Canada
Abstract :
This paper first analyzes faulty scan chain behaviors. In addition to stuck-at faults, we also consider timing faults due to hold time violations Test sequences to determine the fault types in a failing scan chain are presented. This is followed by a presentation of two scan design techniques that simplifies scan chain fault diagnosis for both stuck-at and timing faults
Keywords :
VLSI; boundary scan testing; design for testability; failure analysis; fault diagnosis; flip-flops; logic testing; timing; failing scan chain; fault types; faulty scan chain behaviors; hold time violations; scan chain failures; stuck-at faults; test sequences; timing faults; Circuit faults; Circuit testing; Clocks; Costs; Design methodology; Flip-flops; Latches; Routing; Timing; Wires;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732169
