DocumentCode
2374071
Title
High-level synthesis of data paths with concurrent error detection
Author
Antola, Anna ; Piuri, Vincenzo ; Sami, Mariagiovanna
Author_Institution
Dipt. di Elettronica, Politecnico di Milano, Italy
fYear
1998
fDate
2-4 Nov 1998
Firstpage
292
Lastpage
300
Abstract
High-level synthesis of data paths with concurrent self-checking abilities is discussed to balance redundancy, latency, and checking effectiveness. The nominal and the checking computations are scheduled and allocated contemporaneously by using a force-directed approach to limit the number of redundant units required to achieve detection within the latency of the nominal computation only. Resource sharing between the nominal and the checking computation is used to minimise the redundancy, while keeping error aliasing as reduced as possible
Keywords
application specific integrated circuits; error detection; high level synthesis; integrated circuit design; redundancy; scheduling; checking computations; checking effectiveness; concurrent error detection; data paths; error aliasing; force-directed approach; high-level synthesis; latency; redundancy; redundant units; resource sharing; self-checking abilities; Circuit faults; Concurrent computing; Costs; Delay; Embedded system; Fault tolerance; High level synthesis; Processor scheduling; Redundancy; Resource management;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location
Austin, TX
ISSN
1550-5774
Print_ISBN
0-8186-8832-7
Type
conf
DOI
10.1109/DFTVS.1998.732178
Filename
732178
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