DocumentCode
2374179
Title
Yield enhancement by multi-level linear modeling of non-idealities in an interpolated flash ADC
Author
Boni, Andrea ; Pierazzi, Andrea
Author_Institution
Dipt. di Ingegneria dell´´Inf., Parma Univ., Italy
fYear
1998
fDate
2-4 Nov 1998
Firstpage
326
Lastpage
334
Abstract
The paper discusses a diagnostic technique for interpolated flash A/D converters based on a multi-level linear model. It allows identification of non-ideality sources, such as layout imperfections or thermal gradients, in the first silicon and provides guidance for the improvement of yield by layout refinement, thus outperforming Monte Carlo techniques which do not usually account for layout-related issues
Keywords
analogue-digital conversion; circuit layout CAD; integrated circuit layout; integrated circuit modelling; integrated circuit yield; diagnostic technique; interpolated flash ADC; layout imperfections; layout refinement; multi-level linear modeling; nonidealities; thermal gradients; yield enhancement; Analog-digital conversion; Circuits; Delay; Electronic mail; Interpolation; Low voltage; Monte Carlo methods; Silicon; Statistical analysis; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location
Austin, TX
ISSN
1550-5774
Print_ISBN
0-8186-8832-7
Type
conf
DOI
10.1109/DFTVS.1998.732182
Filename
732182
Link To Document