Tolerating medium latencies on data caches with hardware-based prefetching

Author

Moreno, Edward David ; Kofuji, Sérgio Takeo ; Martins, Carlos Augusto P S

Author_Institution

Dept. of Electron. Eng., Sao Paulo Univ., Brazil

Volume

2

fYear

1997

fDate

25-28 May 1997

Firstpage

720

Abstract

Prefetching caches has been proposed as an important technique to hide and tolerate the average latency of memory accesses by exploiting the overlap of processor computations with data accesses. In this paper, we analyze a single-bus multiprocessor using Stochastic Timed Petri Net (STPN) model to study the effects of various parameters such as latency (memory and network) and degree of prefetching on speed-up of the system and the network contention. Our results indicate that fixed sequential prefetching with degree of prefetching equal to four, would improve the speed-up for medium latencies (64 pcycles with processor of 80 MHz) whenever the probability of useful prefetched data into the buffers is high, superior to 0.5

Keywords

Petri nets; cache storage; performance evaluation; shared memory systems; 80 MHz; data caches; hardware-based prefetching; medium latencies; memory accesses; network contention; processor computations; single-bus multiprocessor; stochastic timed Petri net; Analytical models; Data engineering; Delay; Hardware; High performance computing; Laboratories; Large-scale systems; Petri nets; Prefetching; Stochastic systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on

Conference_Location

St. Johns, Nfld.

ISSN

0840-7789

Print_ISBN

0-7803-3716-6

Type

conf

DOI

10.1109/CCECE.1997.608340

Filename

608340