DocumentCode
2374471
Title
Development and production integration of a submicron tungsten interconnect process
Author
Brown, Kevin C. ; Coniff, John ; Barber, Rob ; Rossen, Rebecca
Author_Institution
Nat. Semicond., Fairchild Res. Center, Santa Clara, CA, USA
fYear
1991
fDate
11-12 Jun 1991
Firstpage
308
Lastpage
311
Abstract
The process characterization, optimization, and production implementation of a photoresist-masked, CVD tungsten metallization scheme is described. Statistical experimental design and response surface methodology were used to improve the manufacturability of the deposition and etch process steps. Repeatable deposition and etch rates have been achieved with anisotropic sidewall profiles. Statistical process control charts illustrating critical dimension control, as well as various monitored deposition and etch parameters are shown to document the performance of the integrated process. Finally defect densities of tungsten and aluminum interconnect are compared to ascertain the relative cleanliness and manufacturability of each process
Keywords
CMOS integrated circuits; chemical vapour deposition; integrated circuit manufacture; metallisation; statistical process control; tungsten; CMOS process; CVD; anisotropic sidewall profiles; critical dimension control; defect densities; deposition rate; etch process; etch rates; metallization scheme; photoresist mask; process characterization; production integration; response surface methodology; statistical experimental design; statistical process control; submicron W interconnect process; Anisotropic magnetoresistance; Condition monitoring; Design for experiments; Etching; Manufacturing processes; Metallization; Process control; Production; Response surface methodology; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
Conference_Location
Santa Clara, CA
Print_ISBN
0-87942-673-X
Type
conf
DOI
10.1109/VMIC.1991.153009
Filename
153009
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