Abstract :
For embedded systems in the digital-convergence era, various functions such as communication, security, audio, video, and recognition, are required in a single device. However, improving the speed of an embedded LSI in the system is difficult because of the significantly increasing power-consumption problems. Heterogeneous parallelism on an SoC has been studied to solve these problems. A power-thrifty architecture, which combines embedded CPUs and special processing cores such as dynamic reconfigurable processors, has been proposed targeting a superior performance per power ratio and functional flexibility. From the viewpoint of programming, a parallelizing compiler and an application program interface(API) have been developed that are suitable for heterogeneous parallelism. The evaluation results of various applications tested using prototype chips and programs will also be discussed.
Keywords :
application program interfaces; embedded systems; multiprocessing systems; parallel processing; parallelising compilers; power aware computing; reconfigurable architectures; system-on-chip; SoC; application program interface; audio functions; communication functions; digital convergence; dynamic reconfigurable processors; embedded CPU; embedded LSI; embedded systems; parallelizing compiler; power ratio; power-consumption problems; power-efficient heterogeneous parallelism; power-thrifty architecture; processing cores; prototype chips; recognition functions; security functions; video functions; Convergence; DVD; Data mining; Energy consumption; Face recognition; Image recognition; MPEG 4 Standard; Modems; Rendering (computer graphics); Speech recognition; Digital Convergence; Heterogeneous Multicore; Parallelizing Compiler and API; SoC;
