Title :
A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS
Author :
Verbruggen, Bob ; Wambacq, Piet ; Kuijk, Maarten ; Van der Plas, Geert
Author_Institution :
IMEC, Leuven
Abstract :
A 5 bit 1.75 GS/s flash ADC is realized in 90 nm CMOS. It uses a comparator array with built-in imbalance and offset calibration to lower power consumption. The SNDR is 30.9 dB at low frequencies and gradually degrades to 28.2 dB at 2 GHz. The ADC occupies 280 mum by 110 mum and draws only 7.6 mA from a 1 V supply yielding an energy efficiency of 0.15 pJ/conversion step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; digital CMOS; flash A/D converter; lower power consumption; power 7.6 mW; Calibration; Capacitance; Clocks; Degradation; Energy consumption; Frequency; Multiplexing; Noise level; Switches; Voltage; ADC; flash; high speed;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585933
