DocumentCode :
2374718
Title :
A 6-bit 5-GSample/s Nyquist A/D converter in 65nm CMOS
Author :
Choi, Michael ; Lee, Jungeun ; Lee, Jungho ; Son, Hongrak
Author_Institution :
Samsung Adv. Inst. of Technol., Yongin
fYear :
2008
fDate :
18-20 June 2008
Firstpage :
16
Lastpage :
17
Abstract :
A 6-bit Nyquist A/D converter (ADC) that converts at 5 GHz is reported. Using a wideband track-and-hold amplifier, array averaging, reset switches on analog signal paths, and phase-adjusted clocking for cascaded comparators, a 6-bit flash ADC achieves better than 5 effective bits for input frequencies up to 2.5 GHz at 5 GSample/s. This ADC does not rely on time interleaving, digital calibration, and post data processing for its dynamic performance. Peak INL and DNL are less than 0.7 LSB and 0.6 LSB, respectively. This ADC consumes about 320 mW from 1.3 V at 5 GSample/s. The chip occupies 0.3 mm2 active area, fabricated in 65 nm CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; sample and hold circuits; wideband amplifiers; CMOS; Nyquist A/D converter; analog signal paths; array averaging; cascaded comparators; digital calibration; frequency 2.5 GHz; frequency 5 GHz; phase-adjusted clocking; post data processing; reset switches; size 65 nm; time interleaving; voltage 1.3 V; wideband track-and-hold amplifier; Bandwidth; Calibration; Clocks; Differential amplifiers; Inductors; Interleaved codes; Phased arrays; Preamplifiers; Sampling methods; Switches; A/D converter; CMOS; Nyquist; THA;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
Type :
conf
DOI :
10.1109/VLSIC.2008.4585934
Filename :
4585934
Link To Document :
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