Title :
A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS
Author :
Nazemi, Ali ; Grace, Carl ; Lewyn, Lanny ; Kobeissy, Bilal ; Agazzi, Oscar ; Voois, Paul ; Abidin, Cindra ; Eaton, George ; Kargar, Mahyar ; Marquez, Cesar ; Ramprasad, Sumant ; Bollo, Federico ; Posse, Vladimir A. ; Wang, Stephen ; Asmanis, Georgios
Author_Institution :
ClariPhy Commun., Inc., Irvine, CA
Abstract :
A 10.3 GS/s ADC with 5 GHz input BW and 6 bit resolution in 90 nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6 dB SNDR) for a 100 MHz input signal and 5.1 ENOB (32.4 dB SNDR) for a 5 GHz input (Nyquist) with phase offset correction across the interleaved array.
Keywords :
CMOS integrated circuits; MMIC amplifiers; analogue-digital conversion; calibration; CMOS; ENOB; digital calibration; frequency 5 GHz; interleaved array; open-loop amplifiers; phase offset correction; size 90 nm; time-interleaved pipelined ADC; Calibration; Circuits; Clocks; Digital signal processing; Energy consumption; Optical amplifiers; Phased arrays; Power dissipation; Resistors; Transceivers;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585935
