Title :
A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme
Author :
Kushida, Keiichi ; Suzuki, Azuma ; Fukano, Gou ; Kawasumi, Atsushi ; Hirabayashi, Osamu ; Takeyama, Yasuhisa ; Sasaki, Takahiko ; Katayama, Akira ; Fujimura, Yuuki ; Yabe, Tomoaki
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation.
Keywords :
CMOS integrated circuits; SRAM chips; amplifiers; memory architecture; CMOS technology; SRAM architecture; cascaded bit line scheme; cell failure rate improvement; hierarchical bit line layer; high density cell; self-write-back sense amplifier; size 65 nm; storage capacity 256 Kbit; voltage 0.7 V; CMOS technology; Circuit stability; Costs; Degradation; Low voltage; MOS devices; Parasitic capacitance; Random access memory; Switches; Testing;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585946
