Title :
PVT-variations and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits
Author :
Khellah, Muhammad ; Kim, Nam Sung ; Ye, Yibin ; Somasekhar, Dinesh ; Karnik, Tanay ; Borkar, Nitin ; Hamzaoglu, Fatih ; Coan, Tom ; Wang, Yih ; Zhang, Kevin ; Webb, Clair ; Vivek De
Author_Institution :
Circuits Res. Lab., Hillsboro, OR
Abstract :
PVT-tolerant and supply noise tracking word-line under-drive circuit, PMOS pass device, and dynamic voltage collapse enable read and write stable diffusion-notch-free (DNF) 6T SRAM cells. Measurements from a 45-nm test-chip show 26X reduction in number of single bit failures using those schemes.
Keywords :
MOS integrated circuits; MOS memory circuits; SRAM chips; cache storage; integrated circuit noise; PMOS pass device; dense cache arrays; diffusion-notch-free SRAM cells; dynamic multi-Vcc circuits; dynamic voltage collapse; supply noise; word-line under-drive circuit; Circuit noise; Circuit stability; Degradation; Frequency conversion; MOS devices; Rails; Random access memory; Regulators; Variable structure systems; Voltage;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585947
