A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers

Author

Lu, Jian-Hao ; Chen, Ke-Hou ; Lee, An-Ming ; Wu, Ting-Ying ; Liu, Shen-Iuan

Author_Institution

Grad. Inst. of Electron. Eng.&Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2008

fDate

18-20 June 2008

Firstpage

56

Lastpage

57

Abstract

A digital near-end crosstalk (NEXT) canceller merged with an analog equalizer for multi-lane serial-link receivers has been realized in 0.13mum CMOS technology. With the proposed sign-sign block least-mean-square (SSB-LMS) circuit, a 5 Gb/s PRBS of 231^mnplus1 suffered from both the channel loss and NEXT for 10-inch FR4 traces is successfully equalized. The measured BER is 10^-12 and the measured maximum peak-to-peak jitter is 49.7 ps. This chip occupies 0.56times0.76 mm² and consumes 177 mW including buffers from a 1.2 V supply.

Keywords

CMOS integrated circuits; equalisers; error statistics; jitter; least mean squares methods; receivers; BER; analog equalizer; maximum peak-to-peak jitter; merged CMOS digital near-end crosstalk canceller; multilane serial-link receivers; power 177 mW; sign-sign block least-mean-square circuit; voltage 1.2 V; CMOS technology; Counting circuits; Crosstalk; Delay; Dielectric measurements; Equalizers; Finite impulse response filter; Semiconductor device measurement; Strontium; Transmission line measurements;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585950

Filename

4585950