Title :
Next generation Intel® micro-architecture (Nehalem) clocking architecture
Author :
Kurd, Nasser ; Douglas, Jonathan ; Mosalikanti, Praveen ; Kumar, Rajesh
Author_Institution :
Intel Corp., Hillsboro, OR
Abstract :
This paper describes the next generation Intelreg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter Intelreg QuickPath interconnect and Intelreg QuickPath memory controller clock generation, and jitter-attenuating DLLs.
Keywords :
clocks; integrated memory circuits; microprocessor chips; phase locked loops; I/O clocking architecture; Intel QuickPath interconnect; Intel QuickPath memory controller clock generation; Intel micro-architecture; Nehalem; PLL; adaptive frequency clocking; analog supply tracking system; jitter-attenuating DLL; Adaptive control; Clocks; Communication system control; Control systems; Frequency; Integrated circuit interconnections; Jitter; Phase locked loops; Programmable control; Voltage; DLL; IA; Intel® QuickPath; PLL; interconnect; memory controller;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585952
