A Current Flow Model for m-Level Diode-Clamped Multilevel Converters

Multilevel converters have gained much attention in recent years since they have been a key technology of power electronics to reach the high power ratings required by many applications. Some topological limitations such as DC side voltage balancing, however, have hindered the use of these converters. One of the steps required to solve these problems is the modeling of such complicated topologies to acquire better and deeper insight into the converter structures that consequently paves the way to design new control systems and strategies. This paper presents novel modeling and analysis approach for m-level diode-clamped multilevel converters. Independent of the modulation strategy, the developed current flow model facilitates the study of the dynamic performance of the converter. Simulation results are also provided to validate the proposed models in special cases for 5-level and 6-level diode clamped multilevel converters. Eventually, utilizing the proposed current flow model, it is proved that the traditional SPWM techniques fail to balance the DC-link capacitor voltages