A 2.5-GHz 860μW charge-recycling fractional-N frequency synthesizer in 130nm CMOS

Author

Park, Dongmin ; Lee, Woojae ; Jeon, Sehyung ; Cho, SeongHwan

Author_Institution

Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2008

fDate

18-20 June 2008

Firstpage

88

Lastpage

89

Abstract

A 1.2 V 2.5 GHz 860 muW fractional-N synthesizer is implemented in 130 nm CMOS. It employs charge recycling technique for implicit DC-DC conversion without using any voltage regulators, and achieves -77dBc/Hz and -113.5 dBc/Hz of phase noise at 100 kHz and 1MHz offset, respectively. Self-biased divider and VCO enables robust operation of the proposed circuit.

Keywords

CMOS integrated circuits; DC-DC power convertors; dividing circuits; frequency synthesizers; phase noise; voltage-controlled oscillators; CMOS integrated circuits; DC-DC conversion; VCO; charge recycling technique; fractional-N synthesizer; frequency 2.5 GHz; frequency synthesizer; phase noise; power 860 muW; self-biased divider; size 130 nm; voltage 1.2 V; Circuits; Energy consumption; Frequency synthesizers; Noise robustness; Phase locked loops; Phase noise; Recycling; Regulators; Voltage; Voltage-controlled oscillators; PLL; charge recycling; fractional; frequency synthesizer; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585963

Filename

4585963