• DocumentCode
    2375279
  • Title

    An H.264/AVC scalable extension and high profile HDTV 1080p encoder chip

  • Author

    Chen, Yi-Hau ; Chuang, Tzu-Der ; Chen, Yu-Jen ; Li, Chung-Te ; Hsu, Chia-Jung ; Chien, Shao-Yi ; Chen, Liang-Gee

  • Author_Institution
    Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Hsinchu
  • fYear
    2008
  • fDate
    18-20 June 2008
  • Firstpage
    104
  • Lastpage
    105
  • Abstract
    The first single-chip H.264/AVC HDTV 1080 p encoder for scalable extension (SVC) with high profile is implemented on a 16.76 mm2 die with 90 nm process. It dissipates 349/439 mW at 120/166 MHz for high profile and SVC encoding. The proposed frame-parallel architecture halves external memory bandwidth and operating frequency. Moreover, the prediction architecture with inter-layer prediction tools are applied to further save 70% external memory bandwidth and 50% internal memory access.
  • Keywords
    high definition television; prediction theory; video coding; frame-parallel architecture; inter-layer prediction tools; prediction architecture; scalable extension encoding; single-chip H.264-AVC HDTV 1080 p encoder; Automatic voltage control; Bandwidth; Encoding; Frequency; HDTV; Heat engines; Pipelines; Scalability; Static VAr compensators; Streaming media;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2008 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-1804-6
  • Electronic_ISBN
    978-1-4244-1805-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2008.4585969
  • Filename
    4585969