A 0.4ps-rms-jitter 1-3GHz ring-oscillator PLL using phase-noise preamplification

A 1-3 GHz tunable multiply-by-8 PLL is implemented in 0.13 mum CMOS and occupies 0.07 mm². A proposed fully-differential Gm-C loop filter structure decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. It achieves Lt 118 dBc/Hz PLL in-band noise, Gt 100 kHz offset and 0.4 ps-RMS jitter (integrated from 3 kHz to 300 MHz offset) for ges2.5 GHz outputs.