A fully logic-process-compatible, 3-transistor, SESO-memory cell featuring 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention

Author

Kameshiro, N. ; Watanabe, T. ; Ishii, T. ; Mine, T. ; Sano, T. ; Ibe, H. ; Akiyama, S. ; Yanagisawa, K. ; Ipposhi, T. ; Iwamatsu, T. ; Takahashi, Y.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo

fYear

2008

fDate

18-20 June 2008

Firstpage

122

Lastpage

123

Abstract

A 1-kb memory-cell array composed of single-electron shut-off (SESO) cells was fabricated with the 90-nm logic process for the first time. It features a 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention. In addition to a logic-compatible cell structure and a write-data caching scheme, a backup latch circuit with SESO transistors for logic application was also proposed.

Keywords

cache storage; flip-flops; radiation hardening (electronics); semiconductor storage; single electron transistors; SESO transistors; SESO-memory cell; backup latch circuit; logic process; logic-compatible cell structure; memory cell array; single-electron shut-off cells; size 90 nm; soft error; storage capacity 1 Kbit; time 100 ms; write-data caching scheme; Capacitors; Electrodes; Identity-based encryption; Laboratories; Latches; Leakage current; Logic arrays; Logic circuits; Logic devices; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585976

Filename

4585976