A Sub-μs wake-up time power gating technique with bypass power line for rush current support

Author

Kawasaki, Ken-Ichi ; Shiota, Tetsuyoshi ; Nakayama, Koichi ; Inoue, Atsuki

Author_Institution

Fujitsu Labs. Ltd., Kawasaki

fYear

2008

fDate

18-20 June 2008

Firstpage

146

Lastpage

147

Abstract

A sub-mus wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and separated power lines bypassing rush current to suppress power supply voltage fluctuations. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90 nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24 mus, the supply voltage fluctuation was suppressed to 2.5 mV.

Keywords

CMOS integrated circuits; low-power electronics; microprocessor chips; power semiconductor devices; system-on-chip; 2M-gate scale circuit; CMOS technology; heterogeneous dual-core microprocessor fabrication; low power SOC; power supply voltage fluctuations; power switches; rush current noise; separated power lines; size 90 nm; time 0.24 mus; voltage 2.5 mV; wake-up time power gating technique; CMOS technology; Circuit noise; Circuit simulation; Laboratories; Leakage current; Power supplies; Solid modeling; Switches; Switching circuits; Voltage fluctuations; power gating; rush current noise; stand-by leakage; wake-up time;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585984

Filename

4585984