Title :
In-situ jitter tolerance measurement technique for Serial I/O
Author :
Jaussi, James E. ; Balamurugan, Ganesh ; Kennedy, Joseph ; O´Mahony, Frank ; Mansuri, Mozhgan ; Mooney, Randy ; Casper, Bryan ; Moon, Un-Ku
Author_Institution :
Intel Corp., Hillsboro, OR
Abstract :
A 10.2-12.5 Gb/s CDR incorporating an on-die jitter modulation circuit that enables in-situ jitter tolerance testing is demonstrated in 65 nm CMOS. Sinusoidal jitter is introduced into the CDR loop by modulating the control voltage of the LC-VCO and is programmable in amplitude and frequency. The modulation frequency range is 340 kHz-104 MHz with modulation amplitudes up to 44 UIpp. The on-die jitter tolerance measurements correlate to conventional external jitter tolerance results within 10% across a 0.73-23.5 MHz range.
Keywords :
CMOS integrated circuits; clocks; jitter; voltage-controlled oscillators; CDR loop; CMOS integrated circuit; LC-VCO; bit rate 10.2 Gbit/s to 12.5 Gbit/s; frequency 340 kHz to 104 MHz; in-situ jitter tolerance testing; jitter tolerance measurement; on-die jitter modulation circuit; serial I/O; sinusoidal jitter; size 65 nm; Amplitude modulation; Charge pumps; Circuit testing; Clocks; Frequency modulation; Jitter; Measurement techniques; Modulation coding; Voltage control; Voltage-controlled oscillators; CDR; Serial I/O; jitter tolerance; self-test and in-situ testing;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585993
