A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

Author

Pozzoni, M. ; Erba, S. ; Viola, P. ; Pisati, M. ; Depaoli, E. ; Sanzogni, D. ; Brama, R. ; Baldi, D. ; Repossi, M. ; Svelto, F.

Author_Institution

STMicroelectronics, Pavia

fYear

2008

fDate

18-20 June 2008

Firstpage

172

Lastpage

173

Abstract

A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm² and consumes 140 mA from 1 V at 8.5 Gb/s.

Keywords

CMOS integrated circuits; decision feedback equalisers; radio receivers; spread spectrum communication; synchronisation; CMOS process; DFE data recovery; DFE receiver; SATA/SAS/FC receiver; SSC tolerant CDR; SSC tracking; bit rate 1.5 Gbit/s to 10 Gbit/s; current 140 mA; eye analysis; self-calibration; serial backplane communication; size 65 nm; spread spectrum clock tracking; voltage 1 V; Backplanes; Clocks; Communication standards; Decision feedback equalizers; Delay; Electronics packaging; Feeds; Frequency; Synthetic aperture sonar; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585995

Filename

4585995