DocumentCode
2376045
Title
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
Author
Klim, Peter ; Barth, John ; Reohr, William ; Dick, David ; Fredeman, Gregory ; Koch, Gary ; Le, Hien ; Khargonekar, Aditya ; Wilcox, Pamela ; Golz, John ; Kuang, JB ; Mathews, Abraham ; Luong, Trong ; Ngo, Hung ; Freese, Ryan ; Hunter, Hillery ; Nelson, E
Author_Institution
IBM Syst. & Technol. Group, Austin, TX
fYear
2008
fDate
18-20 June 2008
Firstpage
206
Lastpage
207
Abstract
We present a 1 MB cache subsystem that integrates 2 GHz embedded DRAM macros, charge pump circuits, a 4 Kb one-time-programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5 GB/s peak system data-rate. The eDRAM employs a programmable pipeline, achieving a 1.8 ns latency.
Keywords
CMOS memory circuits; DRAM chips; UHF integrated circuits; cache storage; read-only storage; system-on-chip; SOI CMOS; bit rate 36.5 Gbit/s; built-in self test circuitry; cache subsystem prototype; charge pump circuits; clock multipliers; embedded DRAM; one-time-programmable ROM; peak system data-rate; programmable pipeline; Automatic testing; Charge pumps; Circuit testing; Clocks; Delay; Pipelines; Prototypes; Random access memory; Read only memory; System testing; SOI; eDRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-1804-6
Electronic_ISBN
978-1-4244-1805-3
Type
conf
DOI
10.1109/VLSIC.2008.4586008
Filename
4586008
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