Title :
A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment
Author :
Nii, K. ; Yabuuchi, M. ; Tsukamoto, Y. ; Ohbayashi, S. ; Oda, Y. ; Usui, K. ; Kawamura, T. ; Tsuboi, N. ; Iwasaki, T. ; Hashimoto, K. ; Makino, H. ; Shinohara, H.
Author_Institution :
Renesas Technol. Corp., Tokyo
Abstract :
We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.
Keywords :
CMOS integrated circuits; SRAM chips; circuit stability; CMOS technology; DVFS environment; dual-port SRAM; dynamic voltage and frequency scaling environment; negative bitline technique; passive resistances; read stability; read/write stabilizing circuitry; replica cell transistors; single-port SRAM; size 45 nm; voltage 0.7 V to 1.3 V; wordline suppression technique; CMOS technology; Circuit simulation; Circuit stability; Circuit testing; Degradation; Electronic mail; Random access memory; Robust stability; Robustness; Voltage; 45nm; 6T; 8T; CMOS; DVFS; SRAM; stability;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4586011
