An integrated and improved dispatching approach to reduce cycle time of wet etch and furnace operations in semiconductor fabrication

The dispatching rules for the process of wet etch and furnace are complex due to the multiple considerations of waiting time constraints, batch size forming, and load balancing. This paper proposes an effective three-stage approach based on multi-factors selection, integrating developed dispatching rules and LR-ratio method, to decide the most appropriate scheduler and sequencing order. To verify the viability of the proposed approach, we conduct an empirical study based on real data collected in a semiconductor manufacturing. A simulation model is constructed and the proposed method is applied for evaluating its performance. Numerical results show that the developed approach can significantly reduce the cycle time by 8% compared to the existing approach.