Cycle time reduction for photolithography area with multi-workstation

In the semiconductor industry, cycle time is a key performance index for a fabrication facility to evaluate its productivity. Because of the unique characteristics of the wafer fabrication, e.g., multiple-reentrance, the photolithography process is a typical bottleneck area that can significantly affect the cycle time. In this study, we propose a two-stage dispatching rule for photolithographic jobs. In the first stage, a heuristic method for workload balance problem is developed based on the concept of choosing the machine with the lowest current and waiting workload in minutes. Further, the heuristic rule is also derived using the concept of smallest setup time (SSU) for sequence dependent setup time problem. Numerical study shows that the two-stage dispatching rule can decrease the mean cycle time from 7% to 10% depending on scenarios, compared to the current practice. Finally, a response surface model is developed to capture the relationships between the mean cycle time, arrival rates, and different scenarios.